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(parent: f8788d8) | patch
iommu/amd: Fix the configuration of GCR3 table root pointer
authorAdrian Huang <ahuang12@lenovo.com>
Fri, 14 Feb 2020 10:44:51 +0000 (18:44 +0800)
committerJoerg Roedel <jroedel@suse.de>
Fri, 28 Feb 2020 15:19:48 +0000 (16:19 +0100)
commitc20f36534666e37858a14e591114d93cc1be0d34
tree5d60298e8c15e3e77c00490c638f03ebe64d4793tree | snapshot
parentf8788d86ab28f61f7b46eb6be375f8a726783636commit | diff
iommu/amd: Fix the configuration of GCR3 table root pointer

The SPA of the GCR3 table root pointer[51:31] masks 20 bits. However,
this requires 21 bits (Please see the AMD IOMMU specification).
This leads to the potential failure when the bit 51 of SPA of
the GCR3 table root pointer is 1'.

Signed-off-by: Adrian Huang <ahuang12@lenovo.com>
Fixes: 52815b75682e2 ("iommu/amd: Add support for IOMMUv2 domain mode")
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/amd_iommu_types.h diff | blob | history
Domain: System / Kernel;