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(parent: 7f3c16c) | patch
[ARM][FIX] Fix vfmal.f16 and vfmsl.f16 operand
authorDiogo N. Sampaio <diogo.sampaio@arm.com>
Fri, 8 Mar 2019 17:11:20 +0000 (17:11 +0000)
committerDiogo N. Sampaio <diogo.sampaio@arm.com>
Fri, 8 Mar 2019 17:11:20 +0000 (17:11 +0000)
commitc20c37ba7f546e0898e09953f03ca2c28ddc7035
treed5a1dde3c2e00799460167457e57d5212ae8c280tree | snapshot
parent7f3c16c0f3178efd2883ceac441aa162728f1726commit | diff
[ARM][FIX] Fix vfmal.f16 and vfmsl.f16 operand

The indexed variant of vfmal.f16 and vfmsl.f16
instructions use the uppser bits of the indexed
operand to store the index (1 bit for the double
variant, 2 bits for the quad).

This limits the usable registers to d0 - d7 or
s0 - s15. This patch enforces this limitation.

Differential Revision: https://reviews.llvm.org/D59021

llvm-svn: 355707
llvm/lib/Target/ARM/ARMInstrNEON.td diff | blob | history
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp diff | blob | history
llvm/test/MC/ARM/armv8a-fpmul-error.s diff | blob | history
Domain: System / Toolchain;