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[RISCV] Define vfadd/vfsub/vfrsub intrinsics.
authorHsiangkai Wang <kai.wang@sifive.com>
Mon, 14 Dec 2020 16:51:07 +0000 (00:51 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Tue, 15 Dec 2020 22:31:47 +0000 (06:31 +0800)
commitc1dac6bac5b808a6554181e4fe214f8c7b8e6c50
tree5338d86aa596fd9caa7f89c100797c79ef6d72e1tree | snapshot
parent903f2950091a8a97778e558a1e6cea08794a12cecommit | diff
[RISCV] Define vfadd/vfsub/vfrsub intrinsics.

Define vfadd/vfsub/vfrsub intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>
Differential Revision: https://reviews.llvm.org/D93291
llvm/include/llvm/IR/IntrinsicsRISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll [new file with mode: 0644] blob
Domain: System / Toolchain;