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(parent: 227dabc) | patch
anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS
authorAnuj Phogat <anuj.phogat@gmail.com>
Thu, 31 May 2018 22:41:53 +0000 (15:41 -0700)
committerAnuj Phogat <anuj.phogat@gmail.com>
Mon, 9 Jul 2018 22:38:42 +0000 (15:38 -0700)
commitc1d8300117891ec87762caa30d14307622c65bcf
treef3ee9eee84887d1c1dd17125f549b36df509679etree | snapshot
parent227dabc2664b886e621de03d9ba82073e2fd16aacommit | diff
anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS

CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
src/intel/vulkan/genX_state.c diff | blob | history
Domain: Graphics System / GL;