drm/vc4: Increase the core clock based on HVS load
authorMaxime Ripard <maxime@cerno.tech>
Wed, 26 May 2021 14:13:02 +0000 (16:13 +0200)
committerDom Cobley <popcornmix@gmail.com>
Mon, 21 Mar 2022 16:03:45 +0000 (16:03 +0000)
commitc16f3c1d77148912e7b8c0e29fd4bca98abc28fc
tree323a37e75207291c81c4308abeeddc8950eb109d
parentd77bc36840a6e8838a6156ade8c1b2db33503b9a
drm/vc4: Increase the core clock based on HVS load

Depending on a given HVS output (HVS to PixelValves) and input (planes
attached to a channel) load, the HVS needs for the core clock to be
raised above its boot time default.

Failing to do so will result in a vblank timeout and a stalled display
pipeline.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
drivers/gpu/drm/vc4/vc4_crtc.c
drivers/gpu/drm/vc4/vc4_drv.h
drivers/gpu/drm/vc4/vc4_kms.c