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(parent: 3650b22) | patch
memory: tegra: Correct la.reg address of seswr
authorNicolin Chen <nicoleotsuka@gmail.com>
Thu, 8 Oct 2020 00:37:42 +0000 (17:37 -0700)
committerKrzysztof Kozlowski <krzk@kernel.org>
Tue, 27 Oct 2020 08:03:56 +0000 (09:03 +0100)
commitc14bea053775e0c79a6fdd2d1b5a1d9de4fbd7c7
tree4872268640f3b9647265c406eb45b6dea7c217c3tree | snapshot
parent3650b228f83adda7e5ee532e2b90429c03f7b9eccommit | diff
memory: tegra: Correct la.reg address of seswr

According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field
[23:16] of register at address 0x3e0 with a reset value of 0x80
at register 0x3e0, while bit-1 of register 0xb98 is for enable
bit of seswr.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20201008003746.25659-2-nicoleotsuka@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
drivers/memory/tegra/tegra210.c diff | blob | history
Domain: System / Kernel;