clk: tegra: Squash sor1 safe/brick/src into a single mux
authorThierry Reding <treding@nvidia.com>
Thu, 9 Jun 2016 15:34:51 +0000 (17:34 +0200)
committerThierry Reding <treding@nvidia.com>
Fri, 17 Jun 2016 15:24:09 +0000 (17:24 +0200)
commitc1273af4b92171731c07acabd004bbb2802d3b44
treed28a434d2cfa3b17817f1596da7111dedfe538ce
parente2f716561b7eb6fd5c5962ee0bdbfc7ce2b21243
clk: tegra: Squash sor1 safe/brick/src into a single mux

The sor1 clock on Tegra210 is structured in the following way:

    +-------+
    | pllp  |---+
    +-------+   |    +--------------+       +-----------+
                +----|              |       | sor_safe  |
    +-------+        |              |       +-----------+
    | plld  |--------|              |             |
    +-------+        |              |       +-----------+
                     |   sor1_src   |-------|           |
    +-------+        |              |       +-----------+
    | plld2 |--------|              |             |
    +-------+        |              |             |
                +----|              |             |
    +-------+   |    +--------------+             |
    | clkm  |---+                           +-----------+
    +-------+        +--------------+       |           |
                     |  sor1_brick  |-------|   sor1    |
                     +--------------+       |           |
                                            +-----------+

This is impractical to represent in a clock tree, though, because there
is no name for the mux that has sor_safe and sor1_src as parents. It is
also much more cumbersome to deal with the additional mux because users
of these clocks (the display driver) would have to juggle with an extra
mux for no real reason.

To simply things, the above is squashed into two muxes instead, so that
it looks like this:

    +-------+
    | pllp  |---+
    +-------+   |    +--------------+       +-----------+
                +----|              |       | sor_safe  |
    +-------+        |              |       +-----------+
    | plld  |--------|              |             |
    +-------+        |              |       +-----------+
                     |   sor1_src   |-------|   sor1    |
    +-------+        |              |       +-----------+
    | plld2 |--------|              |           |   |
    +-------+        |              |           |   |
                +----|              |           |   |
    +-------+   |    +--------------+           |   |
    | clkm  |---+                               |   |
    +-------+        +--------------+           |   |
                     |  sor1_brick  |-----------+---+
                     +--------------+

This still very accurately represents the hardware. Note that sor1 has
sor1_brick as input twice, that's because bit 1 in the mux selects the
sor1_brick irrespective of bit 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-id.h
drivers/clk/tegra/clk-tegra-periph.c