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(parent: 467ed27) | patch
[AArch64][SME] SelectSMETileSlice should also match to 'reg+0' when slice is ADD...
authorSander de Smalen <sander.desmalen@arm.com>
Wed, 22 Mar 2023 16:54:00 +0000 (16:54 +0000)
committerSander de Smalen <sander.desmalen@arm.com>
Fri, 24 Mar 2023 14:37:16 +0000 (14:37 +0000)
commitc0d28d58fafe4480a129298efb36120170f35fa0
tree6892de8a03d0b279bcd2ecfc719412ad69d8aabbtree | snapshot
parent467ed2798772344e2a3b4a8d368575f1f9d1a8c6commit | diff
[AArch64][SME] SelectSMETileSlice should also match to 'reg+0' when slice is ADD with non-constant RHS.

It would decompose an address into a `reg + 0` when the slice was not an ADD,
but when the RHS of the ADD was not a constant, it would simply not match.

This patch fixes that, by always resolving to a `reg + 0` slice.
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll [new file with mode: 0644] blob
Domain: System / Toolchain;