drm/i915: Move VLV/CHV prepare_pll later
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 8 Jul 2015 20:45:52 +0000 (23:45 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 26 Aug 2015 08:22:51 +0000 (10:22 +0200)
commitc0b4c660311c73c8ee4ed0e58b65ae9b4b75276d
tree19fb0bd6c4c53637b4b070a65a3991d3e6821fe6
parent770effb19fbdcb44c6bdacf4a78571d28393f48f
drm/i915: Move VLV/CHV prepare_pll later

With DPIO powergating active on CHV, we can't even access the DPIO PLL
registers until the lane power state overrides have been enabled. That
will happen from the encoder .pre_pll_enable() hook, so move
chv_prepare_pll() to happen after that point, which puts it just before
chv_enable_pll() actually.

Do the same for VLV to avoid accumulating weird differences between the
platforms. Both platforms seem happy with the new arrangement.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c