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(parent: bad6032) | patch
[SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 14 Jan 2020 11:51:09 +0000 (11:51 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 14 Jan 2020 11:51:41 +0000 (11:51 +0000)
commitc05a11108b9a9deb266c3c1758677462df61e05e
treea8e63f33c3d318e1758864d8a027180340fd4201tree | snapshot
parentbad6032bc15fa8d16b67b86ef2b2fe48724e756ecommit | diff
[SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and generic ISD::SHL handling.

As mentioned by @nikic on rGef5debac4302, we can merge the guaranteed bottom zero bits from the shifted value, and then, if a min shift amount is known, zero out the bottom bits as well.
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
llvm/test/CodeGen/X86/combine-shl.ll diff | blob | history
Domain: System / Toolchain;