clk: vt8500: rework wm8650_find_pll_bits()
authorRoman Volkov <rvolkov@v1ros.org>
Tue, 7 Jun 2016 21:56:10 +0000 (00:56 +0300)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 21 Jun 2016 00:47:53 +0000 (17:47 -0700)
commitc03d795beee49ed6e96cf3832c083bf2ecaf1408
tree79c24bbb8cdef50a01c49bcf029cbaa9ed7ca670
parent27a0becc26ba7f84babda8c66170827af1fa308d
clk: vt8500: rework wm8650_find_pll_bits()

PLL clock on WM8650 is calculated in the following way:

M * parent [O1] => / P [O2] => / D [O3]

Where O2 is 600MHz >= (M * parent) / P >= 300MHz.

Current algorithm does not met this requirement, so that the
function may return rates which are not supported by the hardware.

This patch fixes the algorithm and simplifies the code, reducing
the calculation time by ~10000 times (according to usermode app) by
removing the nested loops.

Signed-off-by: Roman Volkov <rvolkov@v1ros.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-vt8500.c