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(parent: bac6a1d) | patch
Fix the incorrect DDR clk freq reporting on 8536DS
authorJason Jin <Jason.jin@freescale.com>
Sat, 27 Sep 2008 06:40:57 +0000 (14:40 +0800)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Tue, 7 Oct 2008 20:37:08 +0000 (15:37 -0500)
commitc0391111c33c22fabeddf8f4ca801ec7645b4f5c
tree38f34ae2b3cdb04300ee0c5afb08e9317c2e5d05tree | snapshot
parentbac6a1d1fa1cd80aa57881fa9c2152b853cd0ed4commit | diff
Fix the incorrect DDR clk freq reporting on 8536DS

On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
cpu/mpc85xx/cpu.c diff | blob | history
cpu/mpc85xx/speed.c diff | blob | history
include/asm-ppc/immap_85xx.h diff | blob | history
include/configs/MPC8536DS.h diff | blob | history
Domain: System / Kernel;