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MIPS: Remove cpu_has_safe_index_cacheops
authorRalf Baechle <ralf@linux-mips.org>
Sat, 2 Jul 2016 08:38:05 +0000 (10:38 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 6 Jul 2016 13:09:36 +0000 (15:09 +0200)
commitc00ab4896ed5f7d89af6f90b809e2c0197c6d170
tree45ffb4c8d875ee0373c8a53e6976df10d1293a93tree | snapshot
parentc683ffe2193b31bba64650fc74d1d6ba254eaafdcommit | diff
MIPS: Remove cpu_has_safe_index_cacheops

Very early versions of the 1004K had an hardware issue that made index
cache ops unsafe so they had to be avoided and hit ops be used instead.
This may significantly slow down cache maintenance operations.  Only
very early FPGA versions of the 1004K were affected so let's get rid
of the workaround which was only implemented for the DMA cache
maintenance operations anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/c-r4k.c diff | blob | history
Domain: System / Kernel;