[AArch64] Also combine vector selects fed by non-i1 SETCCs.
authorAhmed Bougacha <ahmed.bougacha@gmail.com>
Mon, 27 Apr 2015 21:43:12 +0000 (21:43 +0000)
committerAhmed Bougacha <ahmed.bougacha@gmail.com>
Mon, 27 Apr 2015 21:43:12 +0000 (21:43 +0000)
commitc004c60c0a69399e3c2bfa2a63635375871f8b0e
tree79db60df99952fe43e39683e8201140f6be0c513
parentc38498f0469aba6a0fb63d99ad398cdf788c5696
[AArch64] Also combine vector selects fed by non-i1 SETCCs.

After legalization, scalar SETCC has an i32 result type on AArch64.
The i1 requirement seems too conservative, replace it with an assert.

This also means that we now can run after legalization. That should also
be fine, since the ops legalizer runs again after each combine, and
all types created all have the same sizes as the (legal) inputs.

Exposed by r235917; while there, robustize its tests (bsl also uses the
register it defines).

llvm-svn: 235922
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll