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[AArch64] Only enable `foldCSELOfCSEl` DAG combine when x != y
authorchenglin.bi <chenglin.bi@linaro.org>
Wed, 11 Jan 2023 02:44:54 +0000 (10:44 +0800)
committerchenglin.bi <chenglin.bi@linaro.org>
Wed, 11 Jan 2023 02:46:09 +0000 (10:46 +0800)
commitbff34a0a5f9b757ee99bf04f1e4c547bfd33e8f5
tree13ca78dd0b492f4db60d45825add70ec9d384642tree | snapshot
parent069d7d7e4868dd7817b8b0c6858ac2334c1a4d89commit | diff
[AArch64] Only enable `foldCSELOfCSEl` DAG combine when x != y

https://alive2.llvm.org/ce/z/Uy_x_b

Fix: https://github.com/llvm/llvm-project/issues/59902

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D141359
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/pr59902.ll [new file with mode: 0644] blob
Domain: System / Toolchain;