cpufreq: powerpc: add cpufreq transition latency for FSL e500mc SoCs
authorZhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Tue, 18 Mar 2014 05:41:25 +0000 (13:41 +0800)
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>
Thu, 20 Mar 2014 02:37:17 +0000 (03:37 +0100)
commitbfa709bc823fc32ee8dd5220d1711b46078235d8
tree04ef279dd3a82117c9282d77101744dbe3cafbe6
parent0b443ead714f0cba797a7f2476dd756f22b5421e
cpufreq: powerpc: add cpufreq transition latency for FSL e500mc SoCs

According to the data provided by HW Team, at least 12 internal platform
clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs.
This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition
latency to make DFS governors work normally on Freescale e500mc boards.

Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
drivers/cpufreq/ppc-corenet-cpufreq.c