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(parent: 7053065) | patch
[Hexagon] v67+ HVX register pairs should support either direction
authorBrian Cain <bcain@codeaurora.org>
Tue, 14 Aug 2018 21:17:46 +0000 (16:17 -0500)
committerBrian Cain <bcain@quicinc.com>
Fri, 14 Feb 2020 18:43:43 +0000 (12:43 -0600)
commitbf3b86bc2f1020fc1b3a69803e6c3df7ffe8694d
tree895746c49387b464e59df7e4f5fcc6325c51edc1tree | snapshot
parent705306526b5ca7eed2fa28ebf832873cbb5085eccommit | diff
[Hexagon] v67+ HVX register pairs should support either direction

Assembler now permits pairs like 'v0:1', which are encoded
differently from the odd-first pairs like 'v1:0'.

The compiler will require more work to leverage these new register
pairs.
16 files changed:
llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp diff | blob | history
llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonRegisterInfo.td diff | blob | history
llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp diff | blob | history
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp diff | blob | history
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h diff | blob | history
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp diff | blob | history
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp diff | blob | history
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h diff | blob | history
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp diff | blob | history
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h diff | blob | history
llvm/test/CodeGen/Hexagon/swp-sigma.ll diff | blob | history
llvm/test/CodeGen/Hexagon/vect-regpairs.ll [new file with mode: 0644] blob
llvm/test/MC/Hexagon/hvx-swapped-regpairs-alias-neg.s [new file with mode: 0644] blob
llvm/test/MC/Hexagon/hvx-swapped-regpairs.s [new file with mode: 0644] blob
Domain: System / Toolchain;