Fix ldn/stn multiple instructions. Fix testcases with unaligned data.
authorJim Wilson <jim.wilson@linaro.org>
Sat, 22 Apr 2017 23:36:01 +0000 (16:36 -0700)
committerJim Wilson <jim.wilson@linaro.org>
Sat, 22 Apr 2017 23:36:01 +0000 (16:36 -0700)
commitbf1554384b186b448904dbc13ee5374239c88520
treea00f30084ee1fc0c491722bcc67b1939e34a0eb4
parent10f489e57677e670bf980e93896762594e9ad908
Fix ldn/stn multiple instructions.  Fix testcases with unaligned data.

sim/aarch64/
* simulator.c (vec_load): Add M argument.  Rewrite to iterate over
registers based on structure size.
(LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
(LD1_1): Replace with call to vec_load.
(vec_store): Add new M argument.  Rewrite to iterate over registers
based on structure size.
(ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
(ST1_1): Replace with call to vec_store.

sim/testsuite/sim/aarch64/
* fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align
data.
* sumulh.s: Delete unnecessary data alignment.
* stn_single.s: Align data.  Fix unaligned ldr insns.  Adjust cmp
arguments to match change.
* ldn_multiple.s, stn_multiple.s: New.
14 files changed:
sim/aarch64/ChangeLog
sim/aarch64/simulator.c
sim/testsuite/sim/aarch64/ChangeLog
sim/testsuite/sim/aarch64/fcvtz.s
sim/testsuite/sim/aarch64/fstur.s
sim/testsuite/sim/aarch64/ldn_multiple.s [new file with mode: 0644]
sim/testsuite/sim/aarch64/ldn_single.s
sim/testsuite/sim/aarch64/ldnr.s
sim/testsuite/sim/aarch64/mla.s
sim/testsuite/sim/aarch64/mls.s
sim/testsuite/sim/aarch64/stn_multiple.s [new file with mode: 0644]
sim/testsuite/sim/aarch64/stn_single.s
sim/testsuite/sim/aarch64/sumulh.s
sim/testsuite/sim/aarch64/uzp.s