[X86] Make AVX512_512_SET0 XMM16-31 lower to 128-bit XOR when AVX512VL is enabled...
authorCraig Topper <craig.topper@intel.com>
Tue, 31 Oct 2017 06:01:04 +0000 (06:01 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 31 Oct 2017 06:01:04 +0000 (06:01 +0000)
commitbeed653135ea69f58b2eb44a4a26ece40c808a09
tree58c4f03964b609579c71c6b5c5bdd71e6f9568a4
parent21e7b53490a8c01fe5931b643455065591b5f5ba
[X86] Make AVX512_512_SET0 XMM16-31 lower to 128-bit XOR when AVX512VL is enabled. Use 128-bit VLX instruction when VLX is enabled.

Unfortunately, this weakens our ability to do domain fixing when AVX512DQ is not enabled, but it is consistent with our 256-bit behavior.

Maybe we should add custom handling to domain fixing to allow EVEX integer XOR/AND/OR/ANDN to switch to VEX encoded fp instructions if the high registers aren't being used?

llvm-svn: 316978
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/test/CodeGen/X86/avx512-cvt.ll
llvm/test/CodeGen/X86/avx512-shuffles/broadcast-scalar-fp.ll
llvm/test/CodeGen/X86/avx512-shuffles/duplicate-high.ll
llvm/test/CodeGen/X86/avx512-shuffles/duplicate-low.ll
llvm/test/CodeGen/X86/avx512-shuffles/in_lane_permute.ll
llvm/test/CodeGen/X86/avx512-shuffles/permute.ll
llvm/test/CodeGen/X86/avx512-shuffles/shuffle-interleave.ll
llvm/test/CodeGen/X86/avx512-shuffles/shuffle-vec.ll
llvm/test/CodeGen/X86/avx512-shuffles/unpack.ll