Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake
authorLuo, Yuanke <yuanke.luo@intel.com>
Mon, 6 May 2019 08:22:37 +0000 (08:22 +0000)
committerLuo, Yuanke <yuanke.luo@intel.com>
Mon, 6 May 2019 08:22:37 +0000 (08:22 +0000)
commitbeec41c656e7d716fd5755cce12e4934fdced267
treecbb53258bcd3f11adc2ee6a8467def1692b30623
parentfb607580046ed9fe2891151a23375f0c524d29b3
Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake

Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS  instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data.
VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data.
VDPBF16PS: Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
For more details about BF16 isa, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference

Author: LiuTianle

Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, RKSimon, spatel

Reviewed By: craig.topper

Subscribers: kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60550

llvm-svn: 360017
28 files changed:
llvm/include/llvm/IR/IntrinsicsX86.td
llvm/lib/Support/Host.cpp
llvm/lib/Target/X86/X86.td
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/lib/Target/X86/X86IntrinsicsInfo.h
llvm/lib/Target/X86/X86Subtarget.h
test/CodeGen/X86/avx512bf16-intrinsics.ll [new file with mode: 0644]
test/CodeGen/X86/avx512bf16-vl-intrinsics.ll [new file with mode: 0644]
test/MC/Disassembler/X86/avx512bf16-att.txt [new file with mode: 0644]
test/MC/Disassembler/X86/avx512bf16-intel.txt [new file with mode: 0644]
test/MC/Disassembler/X86/avx512bf16vl-att.txt [new file with mode: 0644]
test/MC/Disassembler/X86/avx512bf16vl-intel.txt [new file with mode: 0644]
test/MC/Disassembler/X86/x86-64-avx512bf16-att.txt [new file with mode: 0644]
test/MC/Disassembler/X86/x86-64-avx512bf16-intel.txt [new file with mode: 0644]
test/MC/Disassembler/X86/x86-64-avx512bf16vl-att.txt [new file with mode: 0644]
test/MC/Disassembler/X86/x86-64-avx512bf16vl-intel.txt [new file with mode: 0644]
test/MC/X86/avx512_bf16-encoding.s [new file with mode: 0644]
test/MC/X86/avx512_bf16_vl-encoding.s [new file with mode: 0644]
test/MC/X86/intel-syntax-avx512_bf16.s [new file with mode: 0644]
test/MC/X86/intel-syntax-avx512_bf16_vl.s [new file with mode: 0644]
test/MC/X86/intel-syntax-x86-64-avx512_bf16.s [new file with mode: 0644]
test/MC/X86/intel-syntax-x86-64-avx512_bf16_vl.s [new file with mode: 0644]
test/MC/X86/x86-64-avx512_bf16-encoding.s [new file with mode: 0644]
test/MC/X86/x86-64-avx512_bf16_vl-encoding.s [new file with mode: 0644]