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(parent: bf15f86) | patch
xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.
authorScott Telford <stelford@cadence.com>
Thu, 15 Sep 2016 15:26:45 +0000 (16:26 +0100)
committerMax Filippov <jcmvbkbc@gmail.com>
Mon, 19 Sep 2016 18:51:32 +0000 (11:51 -0700)
commitbebbc4bcf36f015a5a051cc8817b11de209fbe8b
treee0dd6dbdafc17293c491524ce1786a4df5ddc4datree | snapshot
parentbf15f86b343ed894e74fb9c6c944cea1f8f9b654commit | diff
xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.

Add module parameter xilinx_uartps.rx_trigger_level=32 to command line
options for CSP to set Rx watermark for xuartps driver lower than the
default value, to avoid UART overruns at 115200 bps.

Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
arch/xtensa/boot/dts/csp.dts diff | blob | history
Domain: System / Kernel;