[PowerPC] Extend GlobalISel implementation to emit and/or/xor.
authorKai Nacke <kai.peter.nacke@ibm.com>
Fri, 16 Sep 2022 23:55:53 +0000 (23:55 +0000)
committerKai Nacke <kai.peter.nacke@ibm.com>
Mon, 21 Nov 2022 20:08:20 +0000 (20:08 +0000)
commitbe4a1dfbf93dcb837e06bb619b934ed8cf9fd224
tree527ff181bf58ffee6b15f7489b65a48bc213d741
parent535c2da58dd2469dc8b8610443b51e5b10867074
[PowerPC] Extend GlobalISel implementation to emit and/or/xor.

Adds some more code to GlobalISel to enable instruction selection for and/or/xor.

- Makes G_IMPLICIT_DEF, G_CONSTANT, G_AND, G_OR, G_XOR legal for 64bit register size.
- Implement lowerReturn in CallLowering
- Provides mapping of the operands to register banks.
- Adds register info to G_COPY operands.

The utility functions are all only implemented so far to support this use case.
Especially the functions in PPCGenRegisterBankInfo.def are too simple for
general use.

Reviewed By: nemanjai, shchenz, amyk

Differential Revision: https://reviews.llvm.org/D127530
llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def [new file with mode: 0644]
llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical.ll [new file with mode: 0644]