drm/amd/display: Update dram_clock_change_latency for DCN2.1
authorJake Wang <haonan.wang2@amd.com>
Fri, 8 Jan 2021 17:27:51 +0000 (12:27 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 21 Jan 2021 15:46:05 +0000 (10:46 -0500)
commitbdfc6fd6c8df1a9d481c4417df571e94a33168bf
tree17526e786fac06b962dacca6e3bd2353472bcf65
parentacc214bfafbafcd29d5d25d1ede5f11c14ffc147
drm/amd/display: Update dram_clock_change_latency for DCN2.1

[WHY]
dram clock change latencies get updated using ddr4 latency table, but
that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode support.
This may cause a PState hang on high refresh panels with short vblanks
such as on 1080p 360hz or 300hz panels.

[HOW]
Update latency from 23.84 to 11.72.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c