octeontx2-pf: Use PTP HW timestamp counter atomic update feature
authorSai Krishna <saikrishnag@marvell.com>
Mon, 21 Aug 2023 10:36:29 +0000 (16:06 +0530)
committerDavid S. Miller <davem@davemloft.net>
Wed, 23 Aug 2023 07:20:50 +0000 (08:20 +0100)
commitbdf79b128685458fecc42cd8709375d46407dae2
tree46e73888d90467092b2fec69d15965e30baef9e2
parent6176b8c4a19e150c4176b1ed93174e2f5965c4b5
octeontx2-pf: Use PTP HW timestamp counter atomic update feature

Some of the newer silicon versions in CN10K series supports a feature
where in the current PTP timestamp in HW can be updated atomically
without losing any cpu cycles unlike read/modify/write register.
This patch uses this feature so that PTP accuracy can be improved
while adjusting the master offset in HW. There is no need for SW
timecounter when using this feature. So removed references to SW
timecounter wherever appropriate.

Signed-off-by: Sai Krishna <saikrishnag@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
drivers/net/ethernet/marvell/octeontx2/af/ptp.c
drivers/net/ethernet/marvell/octeontx2/af/ptp.h
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c