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(parent: 46eb3c1) | patch
net/mlx5: DR, Fix potential shift wrapping of 32-bit value
authorYevgeny Kliteynik <kliteyn@nvidia.com>
Wed, 20 Jan 2021 00:53:28 +0000 (02:53 +0200)
committerSaeed Mahameed <saeedm@nvidia.com>
Sat, 30 Jan 2021 02:12:34 +0000 (18:12 -0800)
commitbdbc13c204ee3e742289730618002ff9f21109bf
tree2cbf1628d47c845e4e08439a815880bb9b379afdtree | snapshot
parent46eb3c108fe1744d0a6abfda69ef8c1d4f0e92d4commit | diff
net/mlx5: DR, Fix potential shift wrapping of 32-bit value

Fix 32-bit variable shift wrapping in dr_ste_v0_get_miss_addr.

Fixes: 6b93b400aa88 ("net/mlx5: DR, Move STEv0 setters and getters")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c diff | blob | history
Domain: System / Kernel;