drm/i915/icl: Do read-modify-write as needed during MG PLL programming
authorImre Deak <imre.deak@intel.com>
Tue, 19 Jun 2018 16:41:15 +0000 (19:41 +0300)
committerImre Deak <imre.deak@intel.com>
Thu, 21 Jun 2018 16:02:03 +0000 (19:02 +0300)
commitbd99ce085f165a07fe8b33ad04157b91c91b8668
treeecaba334aaf8bfd82afc483d731e8c907fc14f12
parent9fc59bae0f4a8ec3676a9245abed7721b4d3d8c9
drm/i915/icl: Do read-modify-write as needed during MG PLL programming

Some MG PLL registers have fields that need to be preserved at their HW
default or BIOS programmed values. So make sure we preserve them.

v2:
- Add comment to icl_mg_pll_write() explaining the need for register
  masks. (Vandita)
- Fix patchwork checkpatch warning.

v3:
- Rebase on drm-tip.

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com> (v1)
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180619164115.7835-1-imre.deak@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_dpll_mgr.c