[X86] Fix fmul throughput/latency/uops counts
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Sat, 3 Sep 2022 10:10:51 +0000 (11:10 +0100)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Sat, 3 Sep 2022 10:10:51 +0000 (11:10 +0100)
commitbd956b7db398e4ec1a73a3b344a304d6c6630681
tree3a874910c3aae3f9a1ce3ad8c28eeae75e47a765
parent0735200e3f50de1cab4d2fff0ebff9aec52ff074
[X86] Fix fmul throughput/latency/uops counts

Matches numbers from AMD SoG + Agner - should always be on FPU Pipes 0+1, no additional uops for folded instructions and znver1 double pumps 256-bit vectors and is always latency = 4cy for f64 multiplies

Noticed while adding fmul CostKinds support to the x86 cost models in rG0735200e3f50 and znver1 wasn't being flagged as requiring 2uop for 256-bit vectors
12 files changed:
llvm/lib/Target/X86/X86ScheduleZnver1.td
llvm/lib/Target/X86/X86ScheduleZnver2.td
llvm/test/tools/llvm-mca/X86/Znver1/resources-avx1.s
llvm/test/tools/llvm-mca/X86/Znver1/resources-fma.s
llvm/test/tools/llvm-mca/X86/Znver1/resources-sse1.s
llvm/test/tools/llvm-mca/X86/Znver1/resources-sse2.s
llvm/test/tools/llvm-mca/X86/Znver1/resources-x87.s
llvm/test/tools/llvm-mca/X86/Znver2/resources-avx1.s
llvm/test/tools/llvm-mca/X86/Znver2/resources-fma.s
llvm/test/tools/llvm-mca/X86/Znver2/resources-sse1.s
llvm/test/tools/llvm-mca/X86/Znver2/resources-sse2.s
llvm/test/tools/llvm-mca/X86/Znver2/resources-x87.s