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(parent: 9171561) | patch
AMDGPU: Partially directly select llvm.amdgcn.interp.p1.f16
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 31 Dec 2019 20:28:41 +0000 (15:28 -0500)
committerMatt Arsenault <arsenm2@gmail.com>
Wed, 15 Jan 2020 13:58:58 +0000 (08:58 -0500)
commitbd7658a212ebc27a8f7d69666820df33bc8d61f5
tree637ce5c15ff6f600624a91cc16d8ace46fa3f3cbtree | snapshot
parent91715617ad601c6bd953e1c47ecaaf3610de233fcommit | diff
AMDGPU: Partially directly select llvm.amdgcn.interp.p1.f16

The 16 bank LDS case is complicated due to using multiple
instructions. If I attempt to write a pattern for it, the generated
selector incorrectly places the copy to m0 after the first
instruction, so that needs to be separately addressed.

Also fix not gluing the copy to m0 to the second operation in the
second half of the 16 bank lowering.
llvm/lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
llvm/lib/Target/AMDGPU/VOP3Instructions.td diff | blob | history
llvm/test/MC/AMDGPU/vop3.s diff | blob | history
Domain: System / Toolchain;