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author	Simon Dardis <simon.dardis@imgtec.com>
	Thu, 1 Sep 2016 14:53:53 +0000 (14:53 +0000)
committer	Simon Dardis <simon.dardis@imgtec.com>
	Thu, 1 Sep 2016 14:53:53 +0000 (14:53 +0000)
commit	bd2715475702e6b178e8db2101c8335e305ef787
tree	0b29d29a9d1e49e625bba9112a4d500d093b4ffb	tree \| snapshot
parent	fbd3de7851b5874c282c34d9077f470c344e3870	commit \| diff

[mips] interAptiv based generic schedule model

This scheduler describes a processor which covers all MIPS ISAs based
around the interAptiv and P5600 timings.

Reviewers: vkalintiris, dsanders

Differential Revision: https://reviews.llvm.org/D23551

llvm-svn: 280374

19 files changed:

llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td		diff \| blob \| history
llvm/lib/Target/Mips/Mips.td		diff \| blob \| history
llvm/lib/Target/Mips/MipsSchedule.td		diff \| blob \| history
llvm/test/CodeGen/Mips/biggot.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/divrem.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/add.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/and.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/mul.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/not.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/or.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/select-int.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/sub.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/xor.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/longbranch.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/no-odd-spreg.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/prevent-hoisting.ll		diff \| blob \| history
llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll		diff \| blob \| history

Domain: System / Toolchain;

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