RISC-V: Document that V registers are clobbered on syscalls
authorPalmer Dabbelt <palmer@rivosinc.com>
Mon, 19 Jun 2023 19:01:43 +0000 (12:01 -0700)
committerPalmer Dabbelt <palmer@rivosinc.com>
Sat, 1 Jul 2023 14:38:16 +0000 (07:38 -0700)
commitbcc8790057c1f02d20654f68d107973405c1f823
treeace4a5284c9427fa21b0bf095f81b427e13a11f8
parent533925cb760431cb496a8c965cfd765a1a21d37e
RISC-V: Document that V registers are clobbered on syscalls

This is included in the ISA manual, but it's pretty common for bits of
the ISA manual that are actually ABI to change.  So let's document it
explicitly.

Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20230619190142.26498-1-palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/riscv/vector.rst