drm/i915/execlists: Unify CSB access pointers
authorChris Wilson <chris@chris-wilson.co.uk>
Thu, 28 Jun 2018 20:12:07 +0000 (21:12 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Thu, 28 Jun 2018 21:55:06 +0000 (22:55 +0100)
commitbc4237ec8deaaee5f75d1afa91a19bfe6f948c6f
treec03a2ded1ab1ec5a9697c9fed68cfe3c624563ad
parent8ea397fa70be357f52988eb156b324105b286607
drm/i915/execlists: Unify CSB access pointers

Following the removal of the last workarounds, the only CSB mmio access
is for the old vGPU interface. The mmio registers presented by vGPU do
not require forcewake and can be treated as ordinary volatile memory,
i.e. they behave just like the HWSP access just at a different location.
We can reduce the CSB access to a set of read/write/buffer pointers and
treat the various paths identically and not worry about forcewake.
(Forcewake is nightmare for worstcase latency, and we want to process
this all with irqsoff -- no latency allowed!)

v2: Comments, comments, comments. Well, 2 bonus comments.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180628201211.13837-5-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/intel_engine_cs.c
drivers/gpu/drm/i915/intel_lrc.c
drivers/gpu/drm/i915/intel_ringbuffer.h