clk: tegra: Fix sor1_out clock implementation
authorThierry Reding <treding@nvidia.com>
Wed, 30 Aug 2017 10:21:04 +0000 (12:21 +0200)
committerThierry Reding <treding@nvidia.com>
Thu, 19 Oct 2017 14:38:41 +0000 (16:38 +0200)
commitbc2e4d2986e9d2b8a99c16eb8222da2a360a581f
tree68eec3b252a9c773c6155b09d9e3c632a900c653
parent1d7e2c8e5431454f65f0b785f3aa8bdba2ff436d
clk: tegra: Fix sor1_out clock implementation

This clock was previously called sor1_src and was modelled as an input
to the sor1 module clock. However, it's really an output clock that can
be fed either from the safe, the sor1_pad_clkout or the sor1 module
clocks. sor1 itself can take input from either of the display PLLs.

The same implementation for the sor1_out clock is used on Tegra186, so
this nicely lines up both SoC generations to deal with this clock in a
uniform way.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra-periph.c
drivers/clk/tegra/clk-tegra210.c