[PowerPC] Relax register superclasses for paired memops
authorQiu Chaofan <qiucofan@cn.ibm.com>
Fri, 11 Jun 2021 06:51:36 +0000 (14:51 +0800)
committerQiu Chaofan <qiucofan@cn.ibm.com>
Fri, 11 Jun 2021 06:54:03 +0000 (14:54 +0800)
commitbc104fdcecc0da1650177f3587ffe233b37f071b
tree752f0c16514b724fd82919e6caf3dcc7b08a4a37
parent632cbcac79065a62a306dbda7b3a6e1f315e3260
[PowerPC] Relax register superclasses for paired memops

Relaxing superclass constraint for VSX register classes helps reducing
32-byte spills and copies when register pressure is high.

In test case affected, some of them introduces more copies due to new
allocation order. However, this patch should not be the root cause, and
we may be able to fix it in other places of register allocation.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D104006
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll
llvm/test/CodeGen/PowerPC/constant-pool.ll
llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
llvm/test/CodeGen/PowerPC/mma-outer-product.ll
llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
llvm/test/CodeGen/PowerPC/remove-redundant-moves.ll
llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
llvm/test/CodeGen/PowerPC/vsx.ll