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(parent: ccbe0a8) | patch
Allow CP10/CP11 operations on ARMv5/v6
authorRenato Golin <renato.golin@linaro.org>
Mon, 4 Aug 2014 23:21:56 +0000 (23:21 +0000)
committerRenato Golin <renato.golin@linaro.org>
Mon, 4 Aug 2014 23:21:56 +0000 (23:21 +0000)
commitbc0b0378c5832988c7447fb088d228d3ea6cbb59
tree2133bc0b04dd46a5d279c0608fc933f7de8002cbtree | snapshot
parentccbe0a802217d0a422177ebc4649cfab465426c0commit | diff
Allow CP10/CP11 operations on ARMv5/v6

Those registers are VFP/NEON and vector instructions should be used instead,
but old cores rely on those co-processors to enable VFP unwinding. This change
was prompted by the libc++abi's unwinding routine and is also present in many
legacy low-level bare-metal code that we ought to compile/assemble.

Fixing bug PR20025 and allowing PR20529 to proceed with a fix in libc++abi.

llvm-svn: 214802
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp diff | blob | history
Domain: System / Toolchain;