powerpc/e6500: hw tablewalk: clear TID in kernel indirect entries
authorScott Wood <scottwood@freescale.com>
Tue, 20 May 2014 04:04:55 +0000 (23:04 -0500)
committerScott Wood <scottwood@freescale.com>
Fri, 20 Jun 2014 23:48:29 +0000 (18:48 -0500)
commitbbd08c72c6b3344a230e15264d6cd444ed76b958
tree84da147d07a29dd2bad492ac996c9dd23cdde3f8
parent68986c9f0f4552c34c248501eb0c690553866d6e
powerpc/e6500: hw tablewalk: clear TID in kernel indirect entries

Previously TID was being cleared before the tlbsx, but not after.  This
can lead to a multiway hit between a TLB entry with TID=0 (previously
inserted when PID=0) and a TLB entry with TID!=0 that matches PID.
This can theoretically result in undefined behavior, though we probably
get lucky due to the details of the overlap.  It also results in the
inability to use multihit detection to detect other conflicting TLB
entries, as well as poorer TLB utilization due to duplicating kernel
TLB entries.

Rather than try to patch up MAS1 after tlbsx, the entire value is
saved/restored as with MAS2.

I observed a slight improvement in TLB miss performance with this patch
applied.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Reported-by: Ed Swarthout <ed.swarthout@freescale.com>
arch/powerpc/mm/tlb_low_64e.S