[ARM] Improve codegen of volatile load/store of i64
authorVictor Campos <Victor.Campos@arm.com>
Mon, 16 Dec 2019 14:22:15 +0000 (14:22 +0000)
committerVictor Campos <Victor.Campos@arm.com>
Thu, 19 Dec 2019 11:23:01 +0000 (11:23 +0000)
commitbbcf1c3496ce2bd1ed87e8fb15ad896e279633ce
tree58ccd7772e2d72f39c1af6b02f729a5a66be61ad
parenteca0c97a6bca49b493f3387dbd88ad60c852320f
[ARM] Improve codegen of volatile load/store of i64

Summary:
Instead of generating two i32 instructions for each load or store of a volatile
i64 value (two LDRs or STRs), now emit LDRD/STRD.

These improvements cover architectures implementing ARMv5TE or Thumb-2.

Reviewers: dmgreen, efriedma, john.brawn

Reviewed By: efriedma

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70072
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/lib/Target/ARM/ARMInstrThumb2.td
llvm/test/CodeGen/ARM/i64_volatile_load_store.ll [new file with mode: 0644]