[X86][AVX512] Improve lowering of AVX512 test intrinsics
authorUriel Korach <uriel.korach@intel.com>
Mon, 6 Nov 2017 09:22:38 +0000 (09:22 +0000)
committerUriel Korach <uriel.korach@intel.com>
Mon, 6 Nov 2017 09:22:38 +0000 (09:22 +0000)
commitbb86686a8b6f9433954a535f99f23e11b78ca348
tree7b638850534418ef4bb1e38205b3ab3e5ba44bca
parenteb47d95d528b7e1b47137c6ad028ae93526eb548
[X86][AVX512] Improve lowering of AVX512 test intrinsics

Added TESTM and TESTNM to the list of instructions that already zeroing unused upper bits
and does not need the redundant shift left and shift right instructions afterwards.
Added a pattern for TESTM and TESTNM in iselLowering, so now icmp(neq,and(X,Y), 0) goes folds into TESTM
and icmp(eq,and(X,Y), 0) goes folds into TESTNM
This commit is a preparation for lowering the test and testn X86 intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D38732

llvm-svn: 317465
12 files changed:
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/avx512-skx-insert-subvec.ll
llvm/test/CodeGen/X86/avx512bw-vec-test-testn.ll
llvm/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll
llvm/test/CodeGen/X86/avx512f-vec-test-testn.ll
llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
llvm/test/CodeGen/X86/avx512vl-vec-test-testn.ll
llvm/test/CodeGen/X86/compress_expand.ll
llvm/test/CodeGen/X86/masked_gather_scatter.ll
llvm/test/CodeGen/X86/masked_memop.ll
llvm/test/CodeGen/X86/setcc-lowering.ll