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phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets
authorAbel Vesa <abel.vesa@linaro.org>
Wed, 8 Feb 2023 18:00:14 +0000 (20:00 +0200)
committerVinod Koul <vkoul@kernel.org>
Fri, 10 Feb 2023 16:58:00 +0000 (22:28 +0530)
commitbaf172cc04450b9a3845f0f4907c9bc8d717bc58
tree4994d213db8a1d929d0a355f132ae251cf0dda61tree | snapshot
parent354fc6c513ccb459a67c99a57c8d1a837358a001commit | diff
phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets

The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-6-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c diff | blob | history
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h [new file with mode: 0644] blob
Domain: System / Kernel;