RISC-V: KVM: Modify SBI extension handler to return SBI error code
authorAtish Patra <atishp@rivosinc.com>
Sun, 5 Feb 2023 01:15:07 +0000 (17:15 -0800)
committerAnup Patel <anup@brainfault.org>
Tue, 7 Feb 2023 15:05:45 +0000 (20:35 +0530)
commitbae0dfd74e0147cbde332e31b7a71bf6db0eab45
treee0656c98ef308dd5c04be56d8d49f114bdd179a4
parent8cdb8a53857d54fbbabad2593c3c841836e990a9
RISC-V: KVM: Modify SBI extension handler to return SBI error code

Currently, the SBI extension handle is expected to return Linux error code.
The top SBI layer converts the Linux error code to SBI specific error code
that can be returned to guest invoking the SBI calls. This model works
as long as SBI error codes have 1-to-1 mappings between them.
However, that may not be true always. This patch attempts to disassociate
both these error codes by allowing the SBI extension implementation to
return SBI specific error codes as well.

The extension will continue to return the Linux error specific code which
will indicate any problem *with* the extension emulation while the
SBI specific error will indicate the problem *of* the emulation.

Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/kvm_vcpu_sbi.h
arch/riscv/kvm/vcpu_sbi.c
arch/riscv/kvm/vcpu_sbi_base.c
arch/riscv/kvm/vcpu_sbi_hsm.c
arch/riscv/kvm/vcpu_sbi_replace.c
arch/riscv/kvm/vcpu_sbi_v01.c