[RISCV] Store SEW in RISCV vector pseudo instructions in log2 form.
authorCraig Topper <craig.topper@sifive.com>
Sun, 2 May 2021 19:01:18 +0000 (12:01 -0700)
committerCraig Topper <craig.topper@sifive.com>
Sun, 2 May 2021 19:09:20 +0000 (12:09 -0700)
commitba63cdb8f2a5d9ab511c4a58391163869d907110
tree59673abaa25cbc4e2de1075ac93eaa05409cfc19
parent01d27fc408367200f00daad2c2d0918b252acd2c
[RISCV] Store SEW in RISCV vector pseudo instructions in log2 form.

This shrinks the immediate that isel table needs to emit for these
instructions. Hoping this allows me to change OPC_EmitInteger to
use a better variable length encoding for representing negative
numbers. Similar to what was done a few months ago for OPC_CheckInteger.

The alternative encoding uses less bytes for negative numbers, but
increases the number of bytes need to encode 64 which was a very
common number in the RISCV table due to SEW=64. By using Log2 this
becomes 6 and is no longer a problem.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir