[MIPS] Remove an incorrect microMIPS instruction alias
authorSimon Dardis <simon.dardis@gmail.com>
Sun, 8 May 2022 21:23:16 +0000 (22:23 +0100)
committerSimon Dardis <simon.dardis@gmail.com>
Wed, 11 May 2022 22:40:38 +0000 (23:40 +0100)
commitba1c70c69db853485c3f286f470a2efc9a4b7fea
treef9284bf5b9a39b5786d85b5eccf89e64133fda64
parentc2a7904aba465fcaf13bbe2a5772cdeeb88060e5
[MIPS] Remove an incorrect microMIPS instruction alias

The microMIPS instruction set is compatible with the MIPS instruction
set at the assembly level but not in terms of encodings. `nop` in
microMIPS is a special case as it has the same encoding as `nop` for
MIPS.

Fix this error by reducing the usage of NOP in the MIPS backend such
that only that ISA correct variants are produced.

Differential Revision: https://reviews.llvm.org/D124716
16 files changed:
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/lib/Target/Mips/MipsBranchExpansion.cpp
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
llvm/lib/Target/Mips/MipsInstrInfo.cpp
llvm/lib/Target/Mips/MipsInstrInfo.h
llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir