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MIPS: lantiq: Fix bitfield masking
authorPetr Cvek <petrcvekcz@gmail.com>
Thu, 20 Jun 2019 21:39:37 +0000 (23:39 +0200)
committerPaul Burton <paul.burton@mips.com>
Mon, 24 Jun 2019 21:15:04 +0000 (14:15 -0700)
commitba1bc0fcdeaf3bf583c1517bd2e3e29cf223c969
tree360a769a14e66ce74cf8d09062e330964b9bbd3ctree | snapshot
parent7c6747bc2e3da8abb63f69eb724006ca8276ce2dcommit | diff
MIPS: lantiq: Fix bitfield masking

The modification of EXIN register doesn't clean the bitfield before
the writing of a new value. After a few modifications the bitfield would
accumulate only '1's.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com
arch/mips/lantiq/irq.c diff | blob | history
Domain: System / Kernel;