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ASoC: rt5677: Set ADC clock to use PLL and enable ASRC
authorCurtis Malainey <cujomalainey@chromium.org>
Wed, 6 Nov 2019 01:13:35 +0000 (17:13 -0800)
committerMark Brown <broonie@kernel.org>
Mon, 11 Nov 2019 13:02:06 +0000 (13:02 +0000)
commitba0b3a977ecf525231d36f2d9f3a6ea05c35090a
tree341e7425717c32d3e09685b9a54b07732efbb925tree | snapshot
parent55229597a94531726878229ccfcd3fe4ec572dc3commit | diff
ASoC: rt5677: Set ADC clock to use PLL and enable ASRC

Use the PLL to kept the correct 24M clock rate so frequency shift does
not occur when using the DSP VAD.

Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/rt5677.c diff | blob | history
sound/soc/codecs/rt5677.h diff | blob | history
sound/soc/intel/boards/bdw-rt5677.c diff | blob | history
Domain: System / Kernel;