drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 14 Feb 2013 19:53:51 +0000 (21:53 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 19 Feb 2013 23:21:47 +0000 (00:21 +0100)
commitb9e1faa7634e68bfcdff00a8e9378fcb662a7f30
tree09f6b05252a5b336ed6f55fd0ec2c76b98aed910
parent4f7dfb6788dd022446847fbbfbe45e13bedb5be2
drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+

The bit controlling whether PIPE_CONTROL DW/QW write targets
the global GTT or PPGTT moved moved from DW 2 bit 2 to
DW 1 bit 24 on IVB.

I verified on IVB that the fix is in fact effective. Without the fix
none of the scratch writes actually landed in the pipe control page.
With the fix the writes show up correctly.

v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c