ARM: tegra: don't exceed AVP limits when configuring PLLP
authorJimmy Zhang <jimmzhang@nvidia.com>
Fri, 24 Jan 2014 17:37:36 +0000 (10:37 -0700)
committerTom Warren <twarren@nvidia.com>
Mon, 3 Feb 2014 16:46:45 +0000 (09:46 -0700)
commitb9dd6215ce280a460ff182f51e80b7f4bf8b019a
treeb8d28f6e2c5fb42f858fdcdf64bf906315af678f
parent9399e540ca5b984582cddb1936ec44bf2756f8a1
ARM: tegra: don't exceed AVP limits when configuring PLLP

Based on the Tegra TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper limit.

The fix is to set the system clock to CLK_M before initializing PLLP,
and then switch back to PLLP_OUT4, which has an appropriate divider
configured, after PLLP has been configured

Implement this logic in new function tegra30_set_up_pllp(),
which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP
clock switching. Remove the duplicate PLLP setup from pllx_set_rate()
and adjust_pllp_out_freqs().

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
[swarren, significantly refactored the change]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/cpu/arm720t/tegra-common/cpu.c
arch/arm/cpu/arm720t/tegra114/cpu.c
arch/arm/cpu/arm720t/tegra30/cpu.c
arch/arm/cpu/tegra-common/clock.c
arch/arm/cpu/tegra114-common/clock.c
arch/arm/cpu/tegra30-common/clock.c
arch/arm/include/asm/arch-tegra/clk_rst.h
arch/arm/include/asm/arch-tegra/clock.h