RegAlloc: Clear isSSA
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 23 Oct 2020 19:45:43 +0000 (15:45 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 28 Oct 2020 16:02:16 +0000 (12:02 -0400)
commitb9c21d43bb0c9e1a6d51f624f4369c717516a459
treeed686f3d24e056724bcf313093147af738a79e37
parent09c73456837a76a8496edf42732f6e47b35a2bb5
RegAlloc: Clear isSSA

The MIR parser may infer SSA, so -run-pass=regallocgreedy would hit a
verifier error after multiple vreg defs are added.
llvm/lib/CodeGen/RegAllocBasic.cpp
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/CodeGen/RegAllocPBQP.cpp
llvm/test/CodeGen/AMDGPU/greedy-broken-ssa-verifier-error.mir [new file with mode: 0644]