[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C
authorJoe Nash <Joseph.Nash@amd.com>
Wed, 13 Jul 2022 18:14:48 +0000 (14:14 -0400)
committerJoe Nash <Joseph.Nash@amd.com>
Tue, 20 Sep 2022 13:56:28 +0000 (09:56 -0400)
commitb982ba2a6e0f11340b4e75d1d4eba9ff62a81df7
tree99d70c0e5f961c3bf759b1938e1d34f0b8ac47f1
parentfaeb237bac7a303ab09135cf6c35505a85c18de7
[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C

    Due to the encoding changes in GFX11, we had a hack in place that
    disables the use of VGPRs above 128. This patch removes the need for
    that hack.

    We introduce a new register class VGPR_32_Lo128 which is used for 16-bit
    operands of VOP1, VOP2, and VOPC instructions. This register class only has the
    low 128 VGPRs, but is otherwise identical to VGPR_32. Therefore, 16-bit VOP1,
    VOP2, and VOPC instructions are correctly limited to use the first 128
    VGPRs, while the other instructions can freely use all 256.

    We introduce new pseduo-instructions used on GFX11 which have the suffix
    t16 (True 16) to use the VGPR_32_Lo128 register class.

Reviewed By: foad, rampitec, #amdgpu

Differential Revision: https://reviews.llvm.org/D133723
57 files changed:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/SIModeRegister.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
llvm/lib/Target/AMDGPU/VOP1Instructions.td
llvm/lib/Target/AMDGPU/VOP2Instructions.td
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/lib/Target/AMDGPU/VOPCInstructions.td
llvm/lib/Target/AMDGPU/VOPInstructions.td
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir [moved from llvm/test/CodeGen/AMDGPU/gfx10-shrink-mad-fma.mir with 65% similarity]
llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
llvm/test/CodeGen/AMDGPU/true16-ra-f128-fail.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s [new file with mode: 0644]
llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s [new file with mode: 0644]
llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s [new file with mode: 0644]
llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s [new file with mode: 0644]
llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s [new file with mode: 0644]
llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s [new file with mode: 0644]
llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s [new file with mode: 0644]
llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s [new file with mode: 0644]