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(parent: c71716b) | patch
drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH
authorHai Li <hali@codeaurora.org>
Fri, 26 Jun 2015 20:03:26 +0000 (16:03 -0400)
committerRob Clark <robdclark@gmail.com>
Sat, 15 Aug 2015 22:27:16 +0000 (18:27 -0400)
commitb96b3a06d1211ba86674db99a6aafe39ef4cbed2
treeb1bce7da9c4ae8e0ec8d8cd0ef4be3cb55cb343dtree | snapshot
parentc71716b17bc772e9c38f85a4b496bbfac0dd32f0commit | diff
drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH

This change takes advantage of a HW feature that synchronize
flush operation on CTL1 to CTL0, to keep dual DSI pipes in
sync.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c diff | blob | history
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h diff | blob | history
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c diff | blob | history
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c diff | blob | history
Domain: System / Kernel;