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[RISCV] Lower fixed length interleaved accesses via vssegN/vlsegN
authorLuke Lau <luke@igalia.com>
Wed, 1 Mar 2023 18:25:48 +0000 (18:25 +0000)
committerLuke Lau <luke@igalia.com>
Sun, 2 Apr 2023 14:20:21 +0000 (15:20 +0100)
commitb95913e8c3a3521b85d689a358e620d89a4e83de
treed7a742bea7c588437137c262ae603a527cd5225atree | snapshot
parent4f8c1957de5f1ecbb7e1327a36f57e60b285e80bcommit | diff
[RISCV] Lower fixed length interleaved accesses via vssegN/vlsegN

This enables the interleaved access pass on O1 and above, and causes
interleaving/deinterleaving shuffles of fixed length vectors with
stores/loads to be lowered into vssegN/vlsegN.

We need to be careful and make sure that we only lower vsseg/vlseg
whenever we know the fixed vector type will fit within the minimum vlen,
and that the interleaving factor is supported for the given LMUL.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D145085
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVISelLowering.h diff | blob | history
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp diff | blob | history
llvm/test/CodeGen/RISCV/O3-pipeline.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll diff | blob | history
llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll [new file with mode: 0644] blob
llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll [new file with mode: 0644] blob
llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll [new file with mode: 0644] blob
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