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(parent: 02d8ab3) | patch
RISC-V: prefetch.* only take base register with zero-offset for the address
authorKito Cheng <kito.cheng@sifive.com>
Mon, 20 Feb 2023 13:47:01 +0000 (21:47 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Mon, 20 Feb 2023 15:26:28 +0000 (23:26 +0800)
commitb943d5771e1cdaba3004c4ca692ffa9e1a094f8d
tree9056af6899ae2c588adb56ee8c0d2eb87e8fe728tree | snapshot
parent02d8ab3e4e2f3d9dc12157a98c976d6698e71e29commit | diff
RISC-V: prefetch.* only take base register with zero-offset for the address

Catched by running gcc.c-torture/execute/builtin-prefetch-2.c with
-march=rv64gc_zicbop.

gcc/ChangeLog:

* config/riscv/riscv.md (prefetch): Use r instead of p for the
address operand.
(riscv_prefetchi_<mode>): Ditto.
gcc/config/riscv/riscv.md diff | blob | history
Domain: System / Toolchain;